Datasheets |
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Title |
Description |
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| APB to Slave Interface Core |
The APB-to-slave interface converts APB bridge signals to peripheral equivalent signals. |
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| AHB to APB Bridge |
AHB-to-APB Bridge interfaces AHB and APB buses. |
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| AXI Slave |
AXI is a generic interface on slave side and allows connecting user slave modules/devices easily. |
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| CSC |
CSC core is defined as an integral sub-block within a video processing application. |
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| DCT |
The DCT is a transform that converts a signal into its constituent frequency components. |
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| DDR |
DDR is used to interface any industry standard (SDR or DDR) memory device to a host model which drives the core to access SDRAM. |
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| UART |
UART core communicates with 50 MHz processor on one side and serial line on the other side. |
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| DPRAM FIR |
DPRAM Based FIR filter core is configured such that user can change the coefficients at run time. |
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| LUT FIR |
LUT based FIR filters are one of the most basic building blocks used in digital signal processing. |
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| GCR |
The GCR core is widely used in variety of application like video, image processing or display systems. |
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| Gigabit Ethernet (eVC) |
The Gigabit Ethernet eVC can be used to verify any IEEE802.3:2000 and IEEE Draft P802.3ae/D4.0 compliant MAC or PHY device. |
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| HDMI (OVM) |
OVM Ready HDMI UVC encrypted source in e-Language with SystemVerilog interface |
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| I2C (SV & UVC, Alpha) |
I2C SystemVerilog VC is fully configurable and easy to use for both module and system-level verification. |
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| IMR |
IMR (Image Resizing) IP core provides facility to shrink or enlarge images according to user requirement. |
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| AMBA AHB (OVM) |
AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. |
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| GBE (OVM) |
The Gigabit Ethernet OVM Ready VC can be used to verify any IEEE802.3:2000 and IEEE Draft P802.3ae/D4.0 compliant MAC or PHY device. |
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| I2C (OVM) |
I2C OVM Ready VC is fully configurable and easy to use for both module and system-level verification. |
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| PCI (OVM) |
PCI-X OVM Ready VC can be used for verification of any Peripheral Component Interconnect (PCI) agent across all levels of abstraction. |
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| SDIO (OVM) |
SDIO is a master-slave protocol, where SD Host Controller, as a master, performs various operations |
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| SPI4.2 (OVM) |
SPI 4 P2 OVM Ready VC represents the data link layer. |
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| PCI master & target (FPGA tested) |
eInfochips' PCI master + Target core offers functionalities of both the modules PCI master and PCI Target and is compliant to PCI 2.2. |
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| PCI express (eVC) |
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| PCI/PCI-x (eVC) |
PCI-X eVC can be used for verification of any Peripheral Component Interconnect (PCI) agent across all levels of abstraction. |
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| PS2 (eVC, Alpha) |
The PS2 eVC supports only Verilog environment and works with Verilog-XL simulator supported by Specman Elite. |
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| SAS (System C) |
The SAS VC is used for layer wise as well as complete design verification. |
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| Serial ATA (System C) |
The Serial ATA protocol, is a high-speed serial link replacement for parallel ATA for storage applications. |
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| SONET (eVC, Beta) |
The SONET eVC can be used for verification of any Synchronous Optical Network components . |
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| SPI (eVC, Alpha) |
SPI eVC can be used to verify Master or Slave devices following the SPI basic protocol as defined in Motorola’s M68HC11 user manual rev 5.0 |
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| SPI (OVM) |
The SPI test environment provides user generated or random generated data injection to DUT. |
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| SPI 3 |
SPI 3.0 core can be used as a customized bridge solution for Link Layer to PHY Layer devices packet based interface. |
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| SPI 5.0 |
SPI 5 core is a customized bridge solution for Link Layer and PHY Layer device based packet interface |
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| SPI 4 P2 (UVC, Beta) |
The SPI 4 interface is used for packet / cell transfer between physical layer and link layer devices |
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| UWB (System C) |
The UWB VC (Verification Component) has an object-oriented architecture that allows easy extensibility and reusability. |
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| XAUI (UVC) |
The XAUI eVC can be used to verify any IEEE P802.3ae/D4.0 compliant MAC or PHY device. |
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